【 Weak current College 】 common circuit repair basics "five" 】

Third, the BGA package
In the 1990s with the integration of technological progress, equipment improvements and deep sub-micron technologies, LSI, VLSI, ULSI have appeared, silicon-chip integration, on IC packaging requirements more stringent, the dramatic increase in I/O pin count, power consumption is increasing. To meet the development needs, in original packaging variety has added a new varieties — — ball grid array package, hereinafter referred to as BGA (BallGridArrayPackage).
BGA appearance will become CPU, South Bridge, VLSI chip for high density, high-performance, versatility and high i/o pin package. Its features are:
1.I/O pin count while increasing, but the pin spacing than QFP, thereby enhancing the Assembly yield;
2. though it's power consumption increased, but can be controlled collapse BGA chip welding, welding, thus short C4 can improve its electric property:
3. the thickness ratio QFP reduce 1/2 above, the weight more than 3/4;
4. reduce parasitic parameter, signal transmission delay small, use frequency boost;
5. assemble available coplanar welding, high reliability;
6.BGA package still and QFP, PGA, the occupation of the substrate area too large;
Intel Corporation on this kind of integration is very high (up to 300 million in a single chip more transistors), power consumption, a lot of CPU chip, such as the Pentium, PentiumPro, P e n t I u m Ⅱ adopts ceramic pin grid array package CPGA and ceramic ball grid array package CBGA, and housing installation Mini fan cooling, so as to achieve a stable and reliable work of the circuit.
IV. the future of the new packaging technology
BGA packaging ratio QFP is advanced, more than the PGA is good, but it's chip area and packaging area ratio/remains low.
Tessera company on the basis of the BGA did improve, developed another known as μ G A B packaging technology, press the center distance of 0.5mm welding zone, chip area/packaging area ratio of 1: 4 ratio of BGA forwarda big step.
In September 1994 Japan Mitsubishi Electric research a chip area/packaging area = 1: 1.1 package structure, its package size larger than bare chip only a little. In other words, a single IC chip, package size as big, and thus was born a new package, named chip size package, or CSP (ChipSizePackage or ChipScalePackage). CSP package has the following characteristics:
1. meet the LSI chip lead to the increasing needs of the feet;
2. solve the IC bare chip cannot communicate parameter testing and screening of ageing;
3. the packaging area to BGA? to 1/10, delay time down to a very short.
Some people think that when a single moment has not yet reached a variety of chip integration can be highly integrated, high-performance, highly reliable CSP chip (with LSI or IC) and ASIC chip (ASIC) Internet in high-density multilayer substrate surface mounting technology (SMT) assembled a wide variety of electronic components, subsystems, or system. From the idea to produce a multi-chip module MCM (MultiChipModel). It will be on a modern computer, automation, communications and other areas have a significant impact. MCM's features are:
1. package delay time out, easy to implement components of high speed;
2. shrinking machine/component package size and weight, volume, weight is reduced by 1/3;
3. reliability has been greatly increased.
With LSI design technology and process improvements and deep sub-micron technologies and micronized reduced chip size, technology use, people have had multiple LSI chip Assembly in a sophisticated multi-layer wiring of enclosures formed MCM product ideas. Further and produce another idea: bring a variety of chip circuit integrated on a wafer, thus also led package consists of a single tiny chip-level Steering silicon wafer level (waferlevel) package changes, this leads to system-on-chip SOC (SystemOnChip) and computer-on-chip PCOC (PCOnChip).
With the CPU and other ULSI circuit, IC package will also have the appropriate development and packaging forms of progress and will in turn lead to chip technology forward.