Saturday, December 18, 2010

Weak current College】 【pull-up resistance, pull-down resistors / pull current, sink / fan-out coefficient】.

<br> (A) the pull-up resistor: <br> <br> <ol> When the TTL circuits driven COMS circuit, if the TTL circuits outputs high level lower than the minimum COMS circuit high (typically 3.5V), then .you will need in the TTL output connected to La resistance to enhance the value of the output. OC gate circuits must be combined with the pull-up resistor to use. To increase the output pin's driving ability, the SCM pin also often use a pull .-up resistor. In COMS chip, in order to prevent static damage, unused pins cannot be vacant, generally connected to La resistance produces lower input impedance, provide discharge load paths. Polish tube feet dangling easier to accept external electromagnetic interference (MOS devices to .high input impedance, very easy to introduce outside interference). Chip PIN with a pull-up resistor to increase the output level, thereby improving chip input signal noise enhance anti-interference ability. Improving bus anti-electromagnetic interference ability. Tube feet dangling easier .to accept external electromagnetic interference. Long term transmission impedance mismatch can easily lead to reflection interference, plus bottom pull resistance is resistance matching, effective suppression of reflected wave interference. </ ol> <br style="FONT-WEIGHT: bold"> ( .Ii) La resistor selection principles include: <br> <br> <ol> From saving power consumption and chip sink capacity considerations should be large enough: resistance, current small. From ensuring adequate driving current account should be small enough: resistance is small ., and current. For high speed circuit, excessive pull-up resistor may become slow edge. </ ol> <br> Considering the above points, usually choose between 1k to 10k. On the pull-down resistor has a similar reason. < .br> <br> (Iii) the pull-up resistor and pull-low resistor for selection should be considered in conjunction with the switching characteristics and subordinate circuit input properties set, you need to consider several factors: <br> <br> < .ol> Drive capability and power balance. More la resistance, for example, in General, the smaller the pull-up resistor, the more driven, but power consumption increases, design is should be noted that the balance between the two. <br> .Junior circuit driving demand. The same above la resistance, for example, when the output of high level, switching off, pull-up resistor selection should be appropriate to be able to lower the current circuits provide enough. <br> High and low level .setting. Different circuit of high and low level of the threshold level will be different, the resistance should be appropriately set up to ensure that output the correct level. More la resistance, for example, when the output low level, switching on, pull- .up resistor and switching on-resistance divider value should ensure that the zero-level below the threshold. Frequency characteristics. More la resistance, for example, pull-up resistors and transistors drain-source capacitance between level and lower input capacitance between the circuit will .form RC delay, the greater the resistance, the greater the delay. Pull-up resistor setting should take into account the circuit in the demand. </ ol> (Iv) the drop-down resistance of the set of principles and a pull- .up resistor is the same. <br> OC gate output high level is a high-impedance state, its pull-up currents to the pull-up resistor to provide that the input is not greater than 100uA per port, set output drive current of .about 500uA, standard operating voltage is 5V, input level level threshold for 0.8V (below this value is the low level); 2V (high level threshold). <br> Selected pull-up resistor: <br> 500uA x 8.4K = .4.2 is selected than when output to 8.4K dropdown to 0.8V following, this is the minimum resistance value, then no small pulled down. If the output drive current is large, the resistance can be reduced, while guaranteeing the drop-down cannot be .less than 0.8V. <br> When the output of high level, ignoring the tubes of the leakage current, the two input required 200uA <br> 200uA x15K = 3V, pull-up resistor for 3V, outlet pressure drop reaches 2V, this .resistance for maximum resistance, and not on La 2V. Selected 10K available. COMS doors can refer to the 74HC series. <br> Design of the leakage current when the pipe is not ignored, IO actual current in a different level is different, this .is just the principle, summarized as: output high level to feed back of the input, output low level do not output to feed support (otherwise the excess current fed to a cascade of input, higher than the low level threshold is unreliable) <br .>++++++++++++++++++++++++++++++++++++++++++++++< br> .Pull-up resistance: the use of a certain output potential points of resistance and the resistance connected to VDD power supply. Because the output can be viewed as an internal resistance of a voltage source, as the pullup resistor and connection, use the VDD resistor .divider principle (General pull-up resistance than the output of the internal resistance is much greater, as the resistance of size see pull-up resistor selection principles), which will pull the high output potential. <br> <ol> If the level .with OC (-collector, TTL) or OD (open-drain, COMS) output, so not a pull-up resistor is not work, this is very easy to understand, the tube does not have a power will not be output. If .the output current is relatively large, the output level will decrease (circuit has a pull-up resistor, but the resistance is too large, the pressure is too high), you can use a pull-up resistor for current component, the level of ."La high." (That is, and a resistance in the IC's internal pull-up resistor, let it drop down). Of course the tubes need the work online sexual range pull-up resistor is not too small. Will certainly use this .way to achieve door circuit-level matches. <br> </ ol> Note that pull-up resistor is too general a delay caused by output level. (RC delay) <br> General CMOS Gate circuit output cannot give it vacant, are .connected to La resistance set to high level. <br> <br> Drop resistance: and pull-up resistor in principle the same, just go to GND, that level will be pulled down. The drop-down resistor is generally used to set .a low level or impedance matching (anti-echo interference). <br> Pull-up resistance works circuit diagram <br> <br> As shown in the upper part of a Bias Resaitor resistance because it is grounded, so called pull-down .resistors, meaning the circuit nodes A level to low direction (land) La; also, illustration at the bottom of a Bias Resaitor resistance because of power supply (positive), and therefore is called a pull-up resistor, meaning the circuit nodes A .level to high direction (power supply is). Of course, many circuit the pull-up resistor and pull-low resistor for the middle of the 12k resistance is not or cannot see. The figure is RS-485/RS-422 bus, .you can immediately recognize a pull-up resistor and pull-low resistor for meaning. But many circuit only a pull-up resistor or drop-down resistance, and actual or pull-up resistor. <br> <br> Digital circuit in unused .input pins to add a fixed level, through 1k received high level of resistance or grounding. <br> <br> 1. definitions: <br> Pull-up is uncertain signals through a resistive fillet bits in high level that acts as a current .limiting resistor!! drop-down for the same reason! <br> Pull the device into the current, the drop-down is the output current <br> Weak intensity only pull-up resistor of resistance, no strict distinction <br> For .non-collector (or drain) open-circuit output circuits (such as ordinary door circuit) enhance the capacity of the current and the voltage is limited, pull-up resistor features primarily for open-collector output circuit output current channel. <br> .<br> 2. Why use La resistance: <br> General for single-trigger, if IC itself does not have internal resistor to enable single-key accelerators to maintain in the State of not being fired or triggered back to original state, you .must also add a IC external resistor. <br> Digital circuit has three States: high level and low level, and high-impedance state, some applications do not want a high-impedance state, you can use a pull-up resistor or pull .-down resistor in a way that is in a stable state, depending on the design requirements! <br> In general the i / o ports, you can set, not to set up, there is built-in, there is the need to .add the output of the I / O port is similar to a transistor of C, if C then a resistance and power connections, the resistance becomes on C la resistance, that is, if the port normally C for high level, through a resistance and .together, the resistance is called a drop-down resistance, the port usually for low level, the effect to: <br> For example: when a receives a pull-up resistor port is set to lose if the State of his normal to high .level, used to detect low level inputs. <br> Pull-up resistor is used to resolve the bus driver provides current capacity is insufficient. The General argument is current, the drop-down resistor is used to absorb the current, also is to .sink. <br> <br> La currents and sink <br> 1. concepts <br> La currents and sink is a measure of circuit output drive capability (Note: La, irrigation is output, so is the driving ability) of the .parameter, this is generally used in digital circuit. <br> First thing to note here, chip manuals in La, sink is a parameter value that is the chip in the actual circuit allows output of La, irrigation currents of high values (maximum allowed .). And the following to say this concept is the actual values in the circuit. <br> Because digital circuit output only the high and low (0, 1), two-level value, high output, typically provide output load current, which .provides the current value is called "La current"; low level output, usually the output to absorb the load current, which absorb the current value is called the "irrigation (in)-current". <br> For the devices, input current .: <br> Poured into current and currents are entered, poured into current is passive, active or current absorption. If the external current through chip PIN to chip 'into' called sink (to be filled in); <br> Conversely if the .internal current through chip PIN from the chip 'out of' known as La current (pulled) <br> 2. Why is able to measure the output drive capability <br> When logic gate output is a low level, poured into logic gate current .called sink, sink, the larger the output side of a low level. The transistor output characteristic curve you can see, the larger the saturation current perfusion pressure drop, the greater the larger the low level. <br> However, the logic gates of .low level is limited, it has a maximum UOLMAX. When you work in logic gate, and are not allowed to exceed this value, the specification of TTL logic gate provides UOLMAX ≤ 0.4 ~ 0.5V. Therefore, the sink has a limit. < .br> <br> When logic gate output is a high level, the logic gate output current from a logic gate from the current known as La current. La current, output side of the lower high level. This is because the output stage transistor is .internal resistance, resistance, voltage drop makes the output voltage decreases. La current, output side of a high level. <br> However, logic gates, high level there is a certain limit, it has a minimum UOHMIN. When you work in logic .gate, and are not allowed to exceed this value, the specification of TTL logic gate provides UOHMIN ≥ 2.4V. Therefore, the current also has a ceiling. <br> Visible, the output of the current and the sink has a ceiling, high .output, La current causes the output level is lower than UOHMIN; low level output sink will make output level higher than UOLMAX. Therefore, the current and sink reflects the output drive capability. (Chip Lahti, irrigation, the greater the current parameter values, .means that the device can be received more load, because, for example sink is the load to the load, is poured into the greater of-current) <br> <br> Due to the high level input current is small, in the level ., can be generally μA without regard to low-level electrical current is large, in Ma-level. Therefore, often low level of irrigation currents not exceeded there would be no problem. Use fan-out coefficient to description logic gate to drive the same .door, fan-out coefficient No is low level maximum output current and low level maximum ratio of the input current. <br> ======================== .=== <br> In the integrated circuit, current, current output and sink output is a very important concept. <br> Pull the release, output current, output current from the outlet. Irrigation is necessary and sufficient, passive input current, .flows from the output port is absorbing current, active aspiration is to enter the port into the suction and irrigation currents from chip detection tester for electronic circuit through the PIN into the chip's current, the difference is absorbed current is active, the input from the chip .called the absorption of the flow of current. Poured into current is passive, inflows from output is poured into current. <br> La-current is a digital circuit output to load the output current, output sink low level is external to the digital circuit .input current, practical is the input, output current capability. <br> Absorbed current is on input (input slot); and La current (output stream) and sink (output being poured into) is relative to the output. <br> + .++++++++++++++++++++++++++++++++++++< br> Give an intuitive interpretation: <br> <br> .Figure PB0 output 0, LED will light up, the current direction is PB0 to PB0 is also a sink; PB1 to output 1, LED will light up, the current direction is PB1 from PB1 outflow, La currents. <br> + + + .++++++++++++++++++++++++++++++++++< br> In the actual circuit sink is behind the next logic gate input low .level current pooled together and poured into the front logic gate outputs the formation, readers see Figure 18-2-3 self-evident. Obviously it's a test circuit should be shown in Figure 18-2-4 (b) below, input the logic .level is output with access to low level, only sink through the add-in to the power of a potentiometer to adjust the potentiometer, can change the size of the sink, output low level voltage value will also change. <br> <br> .(A)-current load and (b) current load <br> Figure 18-2-3 sink and put the current diagram <br> <br> (A)-current load characteristic curve (b) test circuit <br> Figure .18-2-4-current load characteristic curve and test circuits <br> When the output voltage low level value as sink increases to output low-level maximum <sub style="TEXT-DECORATION: underline"> u when U <sub style .= "TEXT-DECORATION: underline"> OLMAX OL = when the corresponding sink value is defined as output low level current amount of <sub style="TEXT-DECORATION: underline"> OLMAX I value. <br> Different series of logic, .the same series of different models of integrated circuits, the national standard for output low level current maximum specification values of IOLMAX provisions are often different. The more commonly-used values are as follows <br> TTL series IOLMAX = 16mA <br> LSTTL74 series .IOLMAX = 8mA <br> LSTTL54 series IOLMAX = 4mA <br> Fan-out coefficient is description of integrated circuits with NO load capacity of parameter, which is defined for the following 18-2-1) <br> NO = IOLMAX / IILMAX .<br> Which allows for maximum IOLMAX sink, IILMAX is a load doors poured into the current level. <br> No, the larger the description more load on the door. General product requirements No ≥ 8. <br> In determining the fan .-out coefficient, correct calculation of the current value is important, for Figure 18-2-3, followed by the next logic gate input terminal is connected in parallel. When the output is a low level, behind logic gate input stream out of IIL ., due to the current limiting, R1 and parallel side head number is irrelevant. However, when the output is a high level, a change in the direction of the electric current to flow into the input side, behind logic gate input of multiple emitter Transistor .transistor is two parallel. Inflow of IIH is doubled and the number of parallel-to-end headers. For Figure 18-2-3, NOL = 2, and NOH = 3, output low voltage and output in either case, fan-out .coefficient may be different. As a result of the numerical ratio IIL IIH numeric to a much larger, integrated circuits, the contradictions in the main aspects of low level fan-out coefficient. Therefore, we only need to take into account the generally low level .fan-out coefficient. <br> </ sub> </ sub> </ sub>.

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