【 Weak current College 】 ensure signal integrity of the circuit board design standard 】

Signal integrity (SI) problem solving sooner, the higher the efficiency of the design, to avoid in the circuit board design is finished before increasing the termination devices. SI design planning tools and resources, this article explores the signal integrity of the core issues and addressing the issues of SI in several ways, this ignores the technical details of the design process.
1. SI problem

With the IC output switching speed increases, no matter how signal cycle, almost all design have experienced signal integrity problems. Even if you are not experiencing the problem, but as the SI circuit operating frequency increases, the future will certainly encounter signal integrity problems.

Signal integrity problems mainly refers to the signal overshoot and damping Oscillation phenomenon, they mainly IC-driven margin and jump function of time. In other words, even if the wiring topology has not changed, as long as chip speed fast enough, the existing design will also be in a critical state, or stop working. We use two examples to illustrate the signal integrity design is inevitable.

One example: in the field of communications, the leading telecommunications company for voice and data exchange production high-speed circuit board (higher than 500MHz), in which case the cost is not particularly important, so you can try with plywood. This Board can realize the full power of grounding and easily form the circuit, you can also require the use of a large number of discrete termination devices, but the design must be correct, cannot be in a critical state.

SI and EMC experts in wiring before to simulation and calculation, and then, circuit board design can follow a series of very strict design rule, in case of doubt, you can increase the termination devices, in order to get as many SI safety margin. Circuit board actual work process, there are some problems, to this end, through the use of controlled impedance-end connection, you can avoid SI issues. In short, the Super standard design can solve the problem of SI.

Example 2: from cost considerations, the Board is usually limited to four storeys (two-layer inside are the power and ground floor). This greatly limits the role of the impedance control. In addition, the wiring layer, intensified crosstalk, and signal line spacing must also be a minimum to the cloth more printed line. On the other hand, the design engineers must adopt the latest and best CPU, memory and video bus design, the design must consider SI issues.

About wiring, topology and termination method, the engineer can usually be obtained from the manufacturer of a large number of CPU, however, these design guidelines is also necessary to integrate with the manufacturing process. To a large extent, circuit board designer's work than telecommunications designers work hard, because the increase in impedance control and termination devices of a very small space. At this time to fully study and resolve those incomplete signals, while ensuring that the design of the product.

The following describes the design process common SI design guidelines.

2, design the preparatory work before

In the design before you begin, you must be thinking and design strategies in order to guide the choice of such as components, technology selection and circuit board production cost control, etc. For the purposes of the SI, to advance research to form the planning or design guidelines to ensure that design results do not appear obvious SI problems, crosstalk or timing problems. Some design criteria can be used by IC manufacturers, however, chip supplier guidelines (or your own design) there are some limitations, in accordance with such criteria may not meet the design does not require Board SI. If the design rules is easy, it does not require design engineer.

In the actual wiring before, we must first address the following issues, in most cases, these issues affect you aredesigning (or are considering design) of the Board, if the large number of the Board, this work is valuable.

3. circuit boards stacked

Some project teams on the determination of the number of PCB layer have great autonomy, while others project group has no such autonomy, therefore, understand your position is very important. And manufacturing and cost analysis engineer Exchange can determine circuit boards stacked error, or discovery circuit board manufacturing tolerances of opportunity. For example, if you specify a certain level is 50 Ω impedance control, manufacturers how to measure and to ensure that this value?

Other important issues include: the expected manufacturing tolerances? in circuit board expected insulated constant? line width and spacing tolerance of? the grounding and signal layer thickness and spacing of permissible error? all these information can be used in the pre-wiring phase.

Based on these data, you can select the cascading. Note that almost every insert other circuit board or back panel of the PCB has thickness requirements, and most of the circuit board manufacturers can manufacture them in different types of layers has fixed thickness requirements, this will greatly constrained final stack. You may want to work closely with manufacturers to define the number of stack. Impedance control tools should be used for different layers build target impedance range, it is important to take into account the manufacturer manufacturing tolerance and adjacent wiring.

In the signal integrity of ideally, all high-speed node should wiring impedance control the inner layer (such as the ribbon cable), but in fact, engineers must often use to all or part of the outer high-speed node routing. To make the best and keep SI decoupling, should as far as possible to the grounding/power layer placed in pairs. If you can have only one docking formation/power layer, you will have to be. If there is no power layer, by definition you can encounter SI issues. You also may encounter such a situation, that is not defined signal return path before difficult simulation or simulation of the circuit board performance.

4, crosstalk and impedance control

From neighbouring signal line coupling will cause crosstalk and change the signal line impedance.Adjacent parallel signal line coupling analysis may decide between signal lines or various types of signal lines between the "security" or expected spacing (or parallel wiring length). For example, to set the clock to the data signal crosstalk limit node MV, but to maintain parallel signal alignment, you can calculate or simulation, found in any given wiring layer signal between the minimum allowable spacing. At the same time, if the design includes the impedance important node (or the clock or dedicated high-speed memory architecture), you must add the wiring is placed in a layer (or several layers) to get the desired impedance.

5. important high-speed node

Latency and delay clock wiring key factors must be considered. Because of time-critical, this node typically must adopt in order to achieve the best termination devices SI quality. To predetermine the nodes at the same time will adjust the placement of components and cabling needed time to plan to adjust the signal integrity design.

6. technical options

Different driving technology suitable for different tasks. Signal is a point-to-point or point-to-many tap? signal is output from the circuit board or remain in the same circuit board? allowed delay and noise margin? as signal integrity design of common criteria, the conversion speed is slower, the better the signal integrity. 50MHz clock with 500ps rise time is unjustified. A 2-3ns's slew rate control devices speed fast enough to guarantee the quality of the SI, and helps to resolve as output synchronous exchange (SSO) and electromagnetic compatibility (EMC).

In the new FPGA programmable ASIC technology or user-defined, you can find the driver technology superiority. Use these custom (or semi-custom) device, you have great room for the selected drive range and speed. The initial design, to meet the FPGA (or ASIC) design time of the request and determine the appropriate output option, if possible, also include pin selection.

In the design phase, IC suppliers to obtain the appropriate simulation model. In order to effectively cover SI simulation, you will need a SI simulation program and the corresponding simulation model (possibly IBIS model).

Finally, in the pre-wiring and wiring phase you should establish a series of design guidelines, they include: target layer impedance, wiring pitch, towards devices technology, important node topology and termination planning.

7, pre-wiring stage

Pre-wiring for planning of the basic process is the first define the input parameter range (driving range, impedance, track, speed) and the range of possible topology (minimum/maximum length, short length, etc.), and then run every possible combination of simulation, analysis of time series and SI simulation results, and finally found acceptable range of values.

Next, the effort to explain to the PCB layout of the wiring constraints. You can use different software tools to perform this type of "clean" preparatory work, wiring procedures can automatically handle this type of wiring constraints. For most users, the timing information is actually more important than the results of the SI, interconnection simulation results can change the wiring, thereby adjusting the timing signaling pathway.

In other applications, this process can be used to determine and system timing pointer incompatible pin or layout of the device. At this point, it is possible to fully determine the need for manual routing node or nodes that do not require termination. For programmable device and ASIC, at this point you can also adjust the output driver choice, in order to improve design or SI avoid discrete termination devices.

8. after the wiring SI simulation

In General, SI design guidelines difficult to ensure that the actual wiring is complete without an SI or timing problems. Even if the design is guided by the guidelines, unless you can continue automatically check the design, or simply cannot guarantee full compliance with the guidelines, the design is therefore inevitable. After the wiring SI simulation inspection will allow systematically break (or change) the design rules, but this is only because of cost considerations or strict wiring requirements do need work.

Now, using SI simulation engine, simulation of high speed digital PCB (even multi-board systems), automatic shield SI problems and generate accurate "PIN to pin" delay parameter. As long as the input signal is good enough, simulation results are also as good. This makes the device model and circuit board manufacturing parameters determine the accuracy of the simulation results of key factors. Many design engineers will simulation "min" and "maximum" design corner, and then use the related information to solve problems and adjust productivity.

9, after the manufacturing stage

These measures can ensure that the design quality of the SI circuit boards, circuit board Assembly is complete, it is still necessary to circuit board on the test platform, the use of an oscilloscope or TDR (time domain reflectometry) measurements, the real circuit board and simulation of expected results. These metrics can help you improve the model and manufacturing parameters to your next design research to make better (less constraints) decision-making.

10, model options

The article on the model selection, static timing verification engineers may have noticed that, although the device data sheet you can get all the data that you want to build a model is still very difficult. The opposite of SI simulation model, the model is easy, but the model dataare difficult to obtain. In essence, SI model data is the only reliable source of IC suppliers, they must maintain a tacit understanding and design engineers. IBIS model standard provides consistent data carrier, but the IBIS model and quality assurance are costly, IC suppliers on this investment is still needed to promote the role of market demand, and circuit board manufacturer may be the only demand-side market.

11, future technology trends

Vision system in all output can be adjusted to match the wiring impedance or receiving circuit load, system test, SI problems can be addressed through programming, or in accordance with specific technology for the distribution of the IC to adjust the SI circuit boards meet the requirement, this allows for greater tolerance or the hardware configuration of the longer range.

Currently, the industry is also concerned about an SI device technologies, many of these techniques include design good termination device (such as LVDS) and automatic programmable output intensity control and dynamic auto-termination function, the use of these technologies are designed to obtain excellent quality of SI, however, most technology and standard CMOS or TTL logic circuit too much difference, and the co-ordination of existing simulation model is not good.

Therefore, EDA companies also are added to the "easily design" of the Colosseum, the people in the design of the early settlement of SI have done a lot of work, in the future, do not need to use SI experts can solve the problem of automation tools SI. Although the technology has not developed to the level, people are exploring new methods of design, from the "SI and timing wiring" beginning design technology is still in development, it is expected that the next few years will be born new design technology.