Weak current College】 【some electronic hardware development experience】.

<br> Trivial: cost savings <br> A phenomenon: the La high / low resistance, much of the resistance of the relationship is not large, they selected a integer 5K? <br> Comment: the market does not exist on the resistance ., 5K closest is 4.99K (precision: 1%), followed by 5.1K (accuracy 5%), its costs are more than 20% of precision 4.7K high 4 x and 2 x. 20% precision resistor there is only 1, .1.5, 2.2, 3.3, 4.7, 6.8 categories (including 10 integer x); Similarly, 20% precision capacitance is also only a few values above, if you chose other values you must use a higher accuracy, cost is turned over several times, .but does not bring any benefit. Phenomenon II: led what color? I think blue quite special, select it <br> Comments: other red green yellow orange color of a regardless of size (5MM following) package, has been proven for decades, .the price is generally 5 cents, and blue is nearly three or four years before inventing things, technological maturity and stability of supply are less expensive, while prices of four or five times. Currently only the blue led in the colors cannot be used on other .occasions, such as replacing displays video signals, etc. In this logic: 74XX door circuit used up, but too soil, or CPLD, seem much more upscale <br> Comments: 74XX door circuit only longer money, but at least dozens of CPLD ., (GAL / PAL although only a few dollars, but is not recommended). Cost increase N times to say the least, to production, documentation, and more work to add a few times. In 4: our system requirements so high, including .CPU and MEM, FPGA, and so on all the chips are the fastest to selected <br> Comment: in a high-speed system does not work in every part, and the high-speed state devices speed increase a rating, price almost doubled ., in addition to back signal integrity problems brought great negative impact. In five: this Board PCB design requirements, using a fine point of the line, automatic cloth? <br> Comments: automatic routing must occupy the larger PCB area, while producing more .than a manual route many times in the hole in the bulk of great products, PCB manufacturers price taking into account in addition to business factors, is the line width and through-hole number, these are influence to the PCB of the finished product rate and .quantity of bit of consumption, saving the cost of the supplier, to find the reason for the price. In VI: procedure as long as stable, code length, efficiency low point is not critical <br> Comments: CPU speed and memory space is .bought with money, if you write code to spend a few days to improve the efficiency of the program, then from the lower CPU clock speed and reduced storage capacity the cost savings is cost-effective. CPLD / FPGA design is similar. <br> .Trivial II: a low-power design phenomenon: our system is 220V power supply, there is no need to care about power problem <br> Comments: low-power design and not just to save power, more advantage reduces power modules and thermal system .costs, reduced due to current also reduces electromagnetic radiation and thermal noise interference. As the temperature of the device, the device life is extended accordingly (semiconductor devices operating temperature 10 degrees each increase, life is reduced by half) phenomenon II: these bus signals .are used to pull out resistance felt assured some <br> Comments: signal needs to be down for various reasons, but also not all want to pull. Pull-down resistor is a simple input signal, the current or following decades μA, La has .been driven by a signal, its current $ Ma-level, the system often address the 32-bit data, may have 244/245 for bus and other signals that are pulled up, a few Watts of power on the consumption of these resistance up .(do not use 8 cents was once the power of ideas to deal with these few Watts of power). Phenomenon: CPU and FPGA these unused I / O port how? let it empty, later <br> Comments: unused I / O port .if vacant, outsid little interference may be recurrent oscillation input signal, and power consumption for basic MOS device depends on the number of flip gate circuit. If you pull it, each pin will also have μA of current level, so the best thing is set .to output (of course it cannot add other driven signal) in four: the FPGA have left so many doors not finished, you can play! <br> Comments: power consumption and by FGPA use trigger number and flip is proportional to the number of .times, so the same model of FPGA in a different circuit different moments of power may differ by 100 times. Minimize the number of high-speed rollover trigger is to reduce the power consumption of basic FPGA. In five: these small chip power consumption is .low, regardless of <br> Comment: for internal less complex chip power consumption is very difficult to establish, it is mainly composed of PIN on current, no load, one ABT16244 so power consumption is unlikely to 1 Ma, but it is the driver .for each foot to 60 Ma of load (eg match scores of Ohm resistance), ie full load power consumption up to 60 * 16 = 960mA, of course, just supply current is so large, the thermal fell to load. In six: memory .have so much control signal, I use this Board requires only OE and WE signal, movie selection on the ground, so that read operations when the data come out faster. <br> Comments: most storage power consumption when the movie selected valid (no .matter how OE and WE) are selected than tablets is not valid for more than 100 times bigger, so it should be possible to use CS to control chip, and meet other requirements as short films selected pulse width. Phenomenon of seven: how these signals .are overshoot? as long as the match well, you can eliminate <br> Comments: with the exception of a few specific signals (such as 100BASE-T, CML), are overshoot, as long as it is not very large, and not .necessarily need to match, even if the match is not the best to match. Like TTL output impedance 50 ohms, even 20 ohm, if also used such matching resistance, current is largeThat power consumption is unacceptable, and another signal amplitude is so small that .can not be used, besides General signal at the output and the output low level output impedance is not the same, there is no way to do an exact match. So on TTL, LVDS, 422, signal match whenever possible overshoot is acceptable. In .8: reduce power consumption are hardware personnel, and software that's OK <br> Comments: hardware just take a stage, Opera is software, bus on almost every chip access, each signal and almost all of the flip control by the software, if the .software can reduce the number of out-of-core access (using the register variable, use the internal CACHE, etc.), a timely response to interrupt (interrupt are often low level effective with pull-up resistor) and other dispute on specific .measures specifically veneer are to reduce power consumption make a significant contribution. Trivial: System efficiency in one: the clock speed of the CPU can handle 100M 70%, the frequency of 200M fine <br> Comments: System for processing involves a wide range of .factors, in the communication business in its bottlenecks are in the memory, CPU and then quickly, external access faster than that which is vain. Phenomenon II: CPU with a larger CACHE, they should be fast <br> Comments: CACHE increases, and .do not necessarily result in improving the performance of the system, in some cases close CACHE rather than the use of CACHE is also fast. The reason is moved to the data in the CACHE to be reused multiple times will increase the system efficiency. So in .communication systems generally only open data CACHE CACHE-directive, even if open or restricted in some storage space, as part of the stack. It also requires programming to take into account the capacity of the CACHE and the block size, this involves the key code .and the length of the loop body and jump range, if a loop is just a little larger than the CACHE, and then in the repeated cycle, it's not good. In 3: so many tasks it is disruptive or query or disruptive hurry up! .<br> Review: interruption of real-time; but not necessarily fast. If you interrupt a task is particularly high, this did not exit, rear and, after a system crash. If the task number but very frequently, the CPU of a .great effort to access interruption of overhead, very low efficiency, if instead of using query form can significantly improve efficiency, but queries sometimes cannot meet real-time requirements, so the best way is to query the interrupt, ie into a break on the accumulation .of all tasks are processed and then exit. In 4: memory interface timing is the factory default configuration, do not modify <br> Comments: BSP for memory interface settings of the default value is the most conservative parameter settings, the application should be considered .in conjunction with the bus frequency and wait for a reasonable period and other parameters. Sometimes the frequency down but can improve efficiency, such as RAM access cycles is 70ns, bus frequency set for 40M, three cycles of the access time, ie to 75ns; .if bus frequency is 50M, must be set to 4 cycle, actual access time is slower to 80ns. In five: a CPU, it uses two distributed processing, processing capabilities can be doubled <br> Comment: move bricks, two people should be .better than a person's efficiency twice; for a painting, a person can only be counterproductive. Use several CPUs required on business have more understanding to determine and minimize the coordination between the two CPUs, so the price of 1 + 1 as close to 2, .never less than 1. In six: the CPU module with DMA, use it to move data faster surely <br> Comments: real DMA by hardware preemption after start simultaneously at both ends of the bus, in a cycle side reading, over there. .But many embedded CPU DMA is only within the simulation, launch every time before you to do many DMA preparations (set the starting address and length, etc.), when the transfer is often the first to read the chip staging, then write out, .that is, moving data two clock cycles than software to move faster (you don't have to take instructions, no loop jump, extra work), but if a move only a few bytes, but also do a lot of preparatory work, generally .involves a function call, efficiency is not high. So this DMA only on large data blocks. <br> Trivial four: signal integrity in one: these signals are simulation, absolutely no problem <br> Comments: simulation model is not possible to exactly .the same with real, even different batch processing of real differences, they are much less model. Besides the actual circumstances vary, the simulation cannot be exhaustive of all possible, especially the crosstalk. There was a lesson is a veneer only specific length of the .packet is extremely easy to packet loss, and the last reason is the value of the length field is 0xFF, when the data appears in the bus, it interferes with the adjacent WE signal, leading to write not into RAM. Other data will WE interfere ., but interference within an acceptable range, but when 8-bit bus at the same time from 0-1, it is naturally in the vicinity of the signal. The conclusion is the simulation results for informational purposes only, it should remain adequate allowance. .Phenomenon: the data bus 100M should be high-frequency signal, the clock frequency is 8K, is not a big problem <br> Comment: the value of the data bus is normally provided by the control signal or to an edge of the clock signal .to sampling, as long as the debate on the establishment of the edge to keep enough time and hold time, outside this range there is interference or overshoot or won't have much impact (certainly overshoot is best not to exceed the chip can withstand the .maximum voltage value), but the clock signal regardless of how low the frequency (in fact, spectrum range is wide), it's edge is the key, you must ensure that its monotonicity and jump time required in a certain range. Phenomenon: since it .is a digital signal, the more steep edge, of course, is the better <br> Comment: the more steep edge, its spectral range, the more wide, high frequency, the greater part of energy; the higher the frequency of the signal .the easier radiation (such as microwave radio can make the mobile phone, and long-wave radio, many countries do not come out), the more prone to interference level signal, and its wire transmission quality is becoming more and more poor, therefore cannot .be used as low-speed chip chips, using a low speed. In four: In order to guarantee a clean power, target decoupling capacitor is <br> Comments: overall decoupling capacitor, the more power, of course, be more smoothly, but .too much also have disadvantages: waste costs, distribution difficulties, power surge current is too big, and so on. Decoupling capacitor design is critical to the right place for local capacity and, in General, there are indisputable chip manuals on decoupling capacitor design reference ., it is best done by manual. In 5: signal matching really in trouble, how can we match? <br> Comment: the general principle is when the signal in the wire transfer time over the jump time, signal reflection is more important. .Signal generation reflection is due to the uneven line impedance, matching the purpose is to make the driver-side, load impedance of the client, and transmission line become close, but can match well with the signal line on the PCB topology is also a great .relationship, transmission lines on a bifurcation, a hole, a corner, a connector, a different location and ground distance of change and so will produce changes in the impedance, and these factors will enable reflection wave becomes complicated, difficult to match, so high .-speed signal only uses point-to-point manner, as much as possible to reduce the through-hole, corner. <br> Trivial v: reliability design of a phenomenon: this veneer has a small batch production, after a long testing didn .'t find any problem <br> Comments: hardware design and chip applications must comply with the relevant norms, in particular chip manual mentions of all parameters (pressure, I / O voltage range, the electric current, time, temperature, PCB wiring, .power quality, etc.), you cannot rely on test to validate. The company has many products have had painful lesson, products sold a couple of years, IC manufacturers for a production line, our Board would not go out because other people's chip parameters .changed point change, but does not go beyond the scope of the manual. If you have to manual, the changes are not afraid of how he could, if the parameter is beyond the scope of the manual can also be looking for his claims (if .then you can go on the Board, your reliability is even more cattle). In this part of the second: circuit design software such as requirements will not have any problems <br> Comments: hardware on many electrical characteristics directly affected by software control, .but the software is often unexpected, program after what could not be expected. The designer should ensure that no matter what kind of software do hardware should not operate in a short time is permanent damage. In 3: user error problems you can't blame .me <br> Comments: requires users to strictly follow the manual operation is true, but the user is a person, there is a mistake, it cannot be said that touch the wrong one key panic, just insert the wrong one plug. Burning Board .So the user can commit various errors that must be protected. In 4: this is bad because the Board on the side of the Board wrong, nor is it my responsibility <br> Comment: for a variety of external hardware interfaces should have adequate compatibility ., not because the other signals is not working properly, you will break. It is not working properly you should only affect the part relating to function, and other features to work correctly, you should complete the strike, even permanent damage, but once you .have restored the interface should be immediately returned to normal..