Wednesday, January 5, 2011

【 Weak current College 】 8-bit microcontroller architecture design of 】

1. introduction
Micro-controllers (Microcontroller) since the 1970s has been for nearly 30 years has been rapid developments and a wide range of applications. With the rapid development of micro-electronics technology, micro-controller to their good performance, small size, price optimization, complete function, prominent advantages are widely used in household appliances, computing and peripherals, communications, industrial control and automation, intelligent devices and instruments, as in the areas of research, teaching, industrial technologies to transform the most effective tool. From the initial adoption of Princeton structure of simple micro-controller to the now widely used Harvard bus architecture RISC microcontrollers, microcontroller made rapid development.

8-bit microcontroller application number is currently the largest micro-controller, it is by far the most number of companies are committed to working in the market; its market and price competition is very fierce, various multifunctional requirements and different specifications of product innovation is also extremely fast speeds. With the integrated circuits and semiconductor process technology of fast development, FPGA and SOC technology continues to competition and the integration of electronic product design to system performance, power consumption, smaller, cheaper, more reliable, easier direction. Therefore, quickly meet the market demand for cost-effective, low-power, high efficiency of 8-bit microcontroller chip or IPCore became nowadays many companies competitive xiangzhu hotspot.

2. the current 8-bit micro-controller update and design trends

For different microcontroller (MCU) products, not only need to consider different manufacturers MCU price/performance ratio, but also need to consider different directives system application characteristics under the MCU. In response to emerging out of the new intelligent electronics, have been in development for different application's MCU embedded system products [2]. the different manufacturers of MCU products its instruction set, especially the instruction set architecture, such as the market is widely used for MCS51 series and PIC series microcontrollers are using CISC instruction system and RISC instruction set.

Micro controller can be divided in accordance with directives system RISC and CISC and RISC class (RISC-LIKE), etc. Traditional MCS51 controller belonging to CISC-high density, its code, but most of the directive require more clock cycles to complete. RISC-general directive density is low, but instruction is very efficient. Class is a combination of RISC-CISC and RISC advantages. RISC and class RISC are so high efficiency of instruction, from small instruction set of hardwired structure and pipeline structure. Simple instructions that can be used for hard wiring instruction decoding, without the need of using microcode control, improved decoding efficiency. Pipeline structure will directive in several steps, in line fills, the average per instruction (CPI) execution time in 1 clock cycle around [3]. in General, RISC than an equivalent CISC to Fast 50%-70%, while easier to design and error correction.

Thus, on 8-bit microcontroller product development and research design mainly to compatible market has been widely used in the product the customer premise, the improve performance and reduce power consumption in order to adapt to market competition and technology development. The original to CISC instruction system for microcontrollers, in an endless stream of updates series has gradually blend into the RISC concept; for a RISC instruction set of the micro-controller, more still is designed for high performance and low power requirements on its entire infrastructure optimization and continuous improvement, in particular the pipeline structure the most improvement. This article is made in circumstances, mainly discussed the RISC architecture of 8-bit microcontroller product design technology.

3.RISC microprocessor architecture and design principles

Although the industry on RISC processors should have what features still have different views, but various RISC architecture have some common features: (1) use of the Harvard bus architecture, most of the directive in one clock cycle to complete the implementation structure of flowing water; (2) use of independent and simple load/store structure; (3) directive decoding are usually hardwired to achieve instead of micro-decode to speed up execution; (4) most of the directive has a fixed format to simplify instruction encoding and decoding; (5) a smaller set of instructions and a few addressing modes; (6) data channel line, highly parallel processing; (7) the use of large-capacity high-speed register (or known as the register files), try to avoid and speed lower system RAM to Exchange data. As far as possible, the operation data is stored in registers, thus reducing the number of times to access memory. According to the above discussions, the following key from the perspective of the architecture, high-performance, low power consumption, both on the 8-bit RISC microcontrollers in key technologies in the design of the study was conducted.

4. key technology

4.1RISC instruction set of the select

The controller system for use with software programming and hardware design specifications for the interface between closely related to this interface is a set of instructions for micro-controller. Directive architecture (ISA) is a microprocessor hardware and collaborative design. Instruction set must be complete, so that all of the features are reasonably be achieved within the space of the program; and instruction set and must be efficient, so that the frequently used functions can be used relatively few instructions. Therefore, available to the application software development of micro-controller systems must have a complete and efficient instruction set.

Instruction set directly determine the microcontroller's internal hardware structure, but also the user program compiled object code generated by it. Instruction set of the final determination and the whole system needed to program memory and data memory, register variables and memory addressing modes are closely related and restraint. Individual parts and even specific bytes should have a unique address, so that the instruction set correctly on the various ministriesFor purposes of identification or bytes. Therefore, and will have a corresponding a series for different products in different measures: 1) from the address and a corresponding increase of registers to weigh the instruction length; 2) on the instructions in the classification and determine the various directives byte format to simplify operations, control signal decoding logic; 3 increase in the corresponding register) to compensate for the lack of instruction byte length; 4) instruction byte format distribution should take into account the complexity of the corresponding part of the structure and corresponding addressing; 5) memory, the register, whether unified I/O port address. The above list is not exhaustive nor order, should at the same time for analysis. Appropriate measures corresponding to the performance, power consumption, design complexity, should be consolidated.

On the ISA for power analysis should command capacity and instruction execution efficiency aspects into consideration. Instruction set size, register variables, memory addressing, pipeline structure technology selected is and instruction code density are closely linked. The study found that in RISC reduced instruction set of the appropriate increased certain complex instruction is improving code density, guarantee processors for high-performance, low power consumption of feasible methods. So it could produce high command code density of RISC instruction set is a low-power design preferred.

4.2 has the share register of pagination design

RISC design philosophy of the main features of all actions are oriented to the register. Using register-register operation instructions in the data transfer speed, but also a streamlines instruction control logic, shrinking the hard wiring the logical components of the control unit of the chip area.
In the instruction fixed register address bits must limit the number of registers, but the introduction of high-end processors, pagination design concept can be extended addressing range. Segmentation, pagination design thought the fundamental starting point lies in the memory of the linear address into two-dimensional or multi-dimensional address; in the directive only minimum dimension addresses, and use other facilities (such as paragraph, registers, page number, register) used to store high-dimensional address. General will register file into several pages, each page has a fixed size, use only the instruction register page address. In the system register sets a page number registers, by changing its content to switch to a different page register access.

To overcome the simple paging mechanism of shortcomings, usually with a share of pagination design, which not only reduces the directive registers the logical address bits, and at all times be able to access the system registers, at the same time easy to different page register between shares of general-purpose registers to exchange information. Of course also the corresponding logical addresses to physical address mapping methods.

4.3 program space for the paging design

Because and register for the same reason, the directive to adopt complete program space address, also limits the size of the space program, so that space is usually introduced pagination design ideas, at the same time on different pages within the public program area (if the directive is fully consistent with the program length space address request, you do not need this thought), its design concept similar to a share register paging design, this will not repeat them. Unique and register public area is different: the program is in the public area on a different page for the program to jump between platforms.

4.4 pipeline technology

Pipeline design and 8-bit RISC microcontroller architecture are inseparable, the entire system of selection of the core, it merits a direct impact on system performance and power consumption.

Pipelining technology to maximize the use of a micro-controller resources so that each part in each clock cycle to work, greatly improving the efficiency, but because each segment of the pipeline between the strong dependency. If handled inappropriately, instruction run will not reach the expected results, and therefore must be familiar with the production of relevant and transfer issues. One resource conflict, that is, one time in contention for the same feature, usually at the same time access memory, which need to pause a shoot line; the second is data-related conflict, there are three types: RAW, WAR, WAW, resolve the conflict through the use of internal structure or delay a shoot line; third, to control the transfer, i.e. for conflict conditions jump instruction, according to the results determine whether jump to determine the new value of the PC, the result is obtained in the implementation stage, making line loss many performance, the General increase in hardware in advance to obtain the result of the operation to resolve the conflict.

The more long lines, and the transfer of two major problems are also more serious: on the one hand lead to hardware control circuit complexity increases greatly, on the other hand, because the line beat pause, lead to an increase in the CPI value and decrease system performance. Therefore, the longer the pipeline is not better, find a balance between the speed and efficiency are the most important.

In 8-bit RISC microcontroller line design, there are many kinds of programmes. Different programmes in the corresponding area, speed and power consumption. Specific selection you should consider several aspects of fusion. First of all should work by systems and lines of progression rate requirements, depth inferred a variety of specific line structure and the required strict timing; and from the system's power consumption, size, performance, and the pipeline-related and transfer issues caused by the design complexity and considerations, to determine the merits of the various programmes; the final compromise choose the optimal solution.

4.5 low power technology

With the rapid development of the semiconductor industry, integrated into the deep sub-micron stage, microprocessor clock frequency and chip integration, power consumption in many areas of design has become the primary concern, the most prominent is the high performance processor and portable electronic device products.

In the instructions according to the functionality of the system hardware and software co-design, determine instruction architecture, different design starting point as a result of poor design power resultsDon't be too great. Therefore the entire architecture of doubt is a low-power issues should be considered first and foremost, mainly reflects the following aspects: 1) as far as possible according to the functional requirements optimized instruction set, simplified system of decoding unit and unit of execution; 2) through the development of hardware parallelism and functional unit of execution to achieve low-power structure; 3) reasonable settings determine memory, register capacity, reduce the required number of bus; 4) system hardware module Division of each child, as well as the software on different job status on the power of optimization is very important.

5. concluding remarks

In the micro-controller applications increasingly widespread today, on microcontroller made more demanding, want a faster, lower power consumption, low cost, easy to learn and use, as well as the composition of the peripheral devices when the system is less. Therefore, the current number of the most widely applied to an 8-bit microcontroller product development and design of the study is very important. And architecture design is the key to the entire design key, followed by all our work is dependent on the design of architecture. This article is on 8-bit RISC architecture in key technologies should consider issues analysis and discussion, has a certain value and significance of the research.

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