Saturday, January 1, 2011

【 Weak current College 】 digital circuit some quiz 】

1. What is synchronization logic and asynchronous logic, synchronization circuit and asynchronous circuit and what's the difference?
Synchronization logic is fixed between the clock of causation. Asynchronous logic is the clock, there is no fixed relationship between cause and effect.

Circuit design can be classified as synchronization circuit and asynchronous circuit design. Synchronization circuit uses a clock to synchronize the operation of the subsystem, and asynchronous circuits do not use a clock synchronization, the subsystem is the use of special "start" and "complete" signals to synchronize. Due to the asynchronous circuit has the following advantages--no clock skew problems, low power consumption, average efficiency but the worst performance, modularity, composable and reusability--so in recent years research on asynchronous circuit increases rapidly, the publication number to multiply, but IntelPentium4 processor design, began using asynchronous circuit design. V asynchronous circuits mainly combinational logic circuits, used to produce address decoder, FIFO or RAM read/write control signal pulse, its logic output and any clock signals are not related, decoding output produced Burr usually can monitor. Synchronization circuit consists of sequential circuits (registers, and a variety of triggers) and combinational logic circuit circuit, all operations are under strict control of the clock. The sequential circuits share the same clock CLK, and all the state changes are on the rise of the clock (or falling edge).

2. What is a "line and" logic, to achieve it, in the hardware characteristics of the specific requirements on what?

Line and logic are the two output signals can be connected and function. On the hardware, use the door to oc (drain or open collector), since no oc door might sink too large, but burned logic gate, while output port should be added a pull-up resistor. (Line or the pull-down resistors)

3. What is Setup and Holdup time, setup and time is the difference between a holdup.

Setup/holdtime is the test chip on the input signal and the time between the clock signal. Establishment time is the trigger of the clock signal rising edge come before, the same data. The input signal should advance the clock on the rise (rise) T time reaches the chip, the T is establishing time-Setuptime. If not, this data is setuptime cannot be the clock into the trigger, only in the next clock rising edge, data can be driven trigger. Maintain time is the trigger of the clock signal rising edge comes later, the same data. If the holdtime is not enough, the same data cannot be driven trigger.

Build time (SetupTime) and hold time (the Holdtime). Establishment time is before the clock edge, data signal needs remain the same. Maintain time is the clock jump after data signal edge needs remain the same. If you do not meet the establishment and maintenance of time, then the DFF will not correctly sampling the data, the

Stability. If the data signal triggers the clock along the length of time before and after are more established and maintained over time, so the amount of time are individually known as build margin and maintain time margin.

4. What is the phenomenon of competition and adventure? how? how do I get rid of?

In combinational logic, because the doors of the input signal pathway through different delay, lead to reach the door time inconsistent call competition. Produce Burr called adventure. If the Boolean type in contrary signals may be generated competition and adventure. Solution: the first is to add a Boolean type of deleted items, the second is the chip external capacitor.

5. do you know those common logic level? TTL and COMS level can directly interconnect?

Common logic level: 12V, 5V, 3.3V; TTL and CMOS not directly interconnected, as the TTL is 0.3-3.6V, while CMOS are in there at 5V 12V. CMOS output TTL is received can be directlyconnected. TTL output CMOS need received ports and a pull-up resistor received 5V or 12V. Cmos level level respectively: Vih > = 0.7VDD, Vil <=0.3VDD;Voh>=0.9VDD,Vol<=0.1VDD.TTL的为:Vih>=2.0v,Vil<=0.8v;Voh> = 2.4v, Vol < = 0.4v. using ttl cmos can direct drive; plus la, the ttl can be driven cmos.

6, how to solve the metastable.

Metastability is the trigger cannot be a stipulated time period reached a recognizable state. When a trigger to enter metastable, neither prediction of the cell's output level, you cannot predict when output to stability in a correct level. In this stable period, the trigger output some intermediate-level, or may be in a State of oscillation, and this kind of useless output level can be along the signal path of each trigger cascade communications.


1 reduce the system clock

2 use the response faster FF

3 introduce synchronization mechanisms to prevent the spread of metastable

4 improve the clock changes with edge quality, fast clock signal

The key is to devices using better technology and clock cycle of margin.

7, IC design of synchronous and asynchronous reset reset.

In clock synchronous reset reset signal along mining, complete the reset action. Asynchronous reset regardless of the clock, as long as the reset signal meets the condition, you complete the reset action. Asynchronous reset to reset signal requirements is relatively high, no burrs, if its relationship with clockUncertainty, may also appear in metastable.

8, MOORE and MEELEY state machine features.

Moore state machine output is only relevant to the current state value, and only when the clock edge will have a status change .Mealy state machine output not only relevant to the current status values and the current input values, this

9, multiple-domain design, how to handle signal cross-domain.

Different clock signal communication between domains needto be synchronized, so that you can prevent new clock domain first-level triggers of metastable signal to lower the impact that the logic for a single control signal can be used for two-level synchronization, such as level, edge detection and pulse signal can be on many use FIFO, dual-port RAM, handshake signals, etc.

Cross-domain of the signal to go through the Synchronizers, prevent the spread of metastable. For example: clock domain 1 a signal to send to the clock domain 2, then the signal sent to the clock domain 2 before after clock domain 2 synchronizers, in order to enter the clock domain 2. The Synchronizer is a two-level triggers, its clock d as clock domain 2 clock. This is afraid of clock domain 1, the signal may not meet clock domain 2 trigger creation time, taken as a result of metastable because there is no causal relationship between them is asynchronous. This can prevent the spread of metastable but does not guarantee that incoming data mining. So normally only synchronization bits little. Such as the control signal, or address. When the synchronization is address, generally the address should be gray code, because gray code each time just getting a bit every time there is only one Synchronizer at work, so you can reduce the error probability, as in the design of the asynchronous FIFO, read-write address, is to use this method. If two clock domains transfer large amounts of data, you can use asynchronous FIFO to solve the problem.

10, gave reg's setup, hold time, seeking the delay in the middle of combinational logic.


11, clock cycle to T, trigger D1 registers to the output time maximum T1max, minimum T1min. Combinational logic circuit maximum delay is T2max, minimum T2min. Ask, trigger D2 set-up time T3 and maintain time what conditions should be met.


12, gives a general timing circuit diagram, a Tsetup, Tdelay, Tck-> q, the clock delay,write a summary

Set maximum clock, at the same time gives the expression.



13, says that static, dynamic, and disadvantages of a time series model.

Static timing analysis using exhaustive analysis method to extract the entire circuit of all time-path, calculating signal in these path propagation delay, check the signal of building and maintaining time timing requirements are met, through the maximum path delay and minimum path delay analysis, identify constraints against timing error. It does not need to enter the vector can exhaust all path and run very fast and consume less memory, not only on chip design full time sequence function check, and timing analysis can also be used to optimize the design of the result, therefore, static timing analysis has increasingly been used to validate digital integrated circuit design.

Dynamic temporal simulation is usually of simulation, because it is not possible to produce a complete test vectors, override the gate-level netlist of each path. Therefore in dynamic time-series analysis, there is no way to expose some path timing issues that may exist;

14, a four-level Mux, of which the second level of the signal as to how to improve the key signal timing.

Key: the second level of the signal on to the final output level output, bearing in mind the modify movie selected signal, to ensure that its priority has not been modified.

15. why a standard inverter in P tube width length ratio than N tube width length ratio?

And the carrier pipe is concerned, P, N void conductive tube electronic conductive, electronic migration rate is larger than the hole, the same electric field, the current is greater than N-P tube, thus to increase the width of the P tube length ratio, symmetric, so you can make both rise time fall time equivalent, high and low level of noise, like time, charge-discharge equal

16, latch and register the difference, why now use register. behavioral description how latch.

Latch is level-triggered, the register is the edge trigger, register at the same clock edge triggered the action, in line with the synchronization circuit design ideas, and the latch is asynchronous circuit design, often leads to time-series analysis difficult, not appropriate for the application of the waste is large latch chip resources.


Non-blocking assignment: block assignment statement to assign values at the same time, generally used to describe the sequential circuits

Block assignment: after completion of the assignment statement in order to do the next sentence, generally used in Combinatorial logic description

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