Weak current College】 【TTL and CMOS level / OC door】.

<br> A. TTL <br> TTL IC's main type as Transistor-transistor logic gate (transistor-transistor logic gate), the most used TTL 5V power supply. <br> 1. output Uoh and output low level Uol <br> .Uoh ≥ 2.4V, Uol ≤ 0.4V <br> 2. Enter the input high level and low level <br> Uih ≥ 2.0V, Uil ≤ 0.8V <br> <br> Second. CMOS <br> CMOS circuit is voltage .control devices, input resistance significantly, interfering signal is very sensitive, so the unused input should not be open circuit, received, or power. The advantages of CMOS circuit is noise wide, static power consumption is very small. <br> 1. output .Uoh and output low level Uol <br> Uoh ≈ VCC, Uol ≈ GND <br> 2. Enter high level Uoh and enter low level Uol <br> Uih ≥ 0.7VCC, Uil ≤ 0.2VCC (VCC, GND power supply voltage to .ground) <br> As can be seen from above: <br> In the same 5V power supply voltage, COMS circuit can direct drive TTL, because CMOS output greater than 2.0V, output low level less than 0.8V; TTL circuits cannot directly .driving CMOS circuits, the TTL is greater than the output, if falls 2.4V 2.4V ~ 3.5V, CMOS circuit could not be detected by the high level and low level less than 0.4V meets the demands, so in TTL circuits driven COMS circuit .requires adding a pull-up resistor. If a different voltage power supply, or through the above methods. <br> If the circuit has glow COMS circuit to drive 5V CMOS circuits, such as 74HC SCM to drive 3.3V, which have the following .methods to resolve, the simplest is to direct the 74HC swap 74HCT (74 series of input and output are described below) chip, because 3.3V CMOS can direct drive 5V TTL circuits; or plus voltage conversion chips; there is a single-chip i ./ o port is set to open drain, then add the pull-up resistor to 5V, such cases have adjusted according to the actual situation, the resistive size to ensure that the signal rise time. <br> <br> Introduction to the series .of three .74 <br> 74 series can be said is that we always in contact with the most chips, 74 series is divided into a number, but we usually use the most is the following: 74LS, 74HC, 74HCT these three, the .three series in the level of difference is as follows: <br> Input level output level <br> TTL TTL 74LS <br> 74HC COMS-COMS-level <br> COMS-TTL 74HCT <br> <br> + + + + .++++++++++++++++++++++++++++++++< br> TTL and CMOS level <br> 1, TTL level (what is TTL .-level): <br> Output> 2.4V, output low level <0.4V. At room temperature, is the General output, output low level 3.5V is 0.2V. Minimum input high level and low level: input high level .> = 2.0V, input low level <= 0.8V, noise is 0.4V. <br> <br> 2, CMOS level: <br> 1 logic level voltage close to the power supply voltage, 0 logic level close to .0V. But with a very wide noise. <br> <br> 3, level conversion circuit: <br> Because the TTL and COMS of level of value is not the same (5v ttl cmos 3.3v <==>) .so interlinked requires level conversion: is to use two resistance on the level of partial pressure, nothing esoteric things. <br> <br> 4, OC, the collector circuit, OD door that drain valve circuit must be external pull-up resistor and .the power to switch level as high or low level. Otherwise, it is generally only used as a switch voltage and high current loads, so it is called the driver door circuit. <br> <br> 5, TTL and COMS circuit: < .br> 1) TTL circuits is the current controller, and CMOS circuit is voltage control devices. <br> 2) TTL circuits of speed, transmission delay time is short (5-10ns), but power consumption. COMS circuit slow propagation delay time .(25-50ns), low power consumption. COMS circuit itself power and input signal pulse frequency, the higher the frequency the more thermal, chip set, this is normal. <br> 3) COMS circuit of lock-in effect: <br .> COMS circuit due to the current input is too big, sharp increase within the current unless cut off power supply, electric current has been increased. This effect is lock-in effect. When you have lock-in effect, the COMS of internal current .40mA above can be achieved easily burnt chip. <br> Defensive measures: 1) in the input and output plus clamp circuit, the input and output not exceeding the voltage does not exceed the prescribed. <br> 2) chip power input with decoupling .circuit to prevent the VDD-high-pressure moments occurred. <br> 3) and the VDD power supply current limiting resistor between, even with large currents do not let it go. <br> 4) when the system is composed of several power .supply separately, switch to the following order: on, first open the COMS Ruth power, then turn on the input signal and load of the power supply, shut down, turn off the input signal and power to the load, and then turn off the .power to the COMS circuit. <br> <br> 6, COMS circuit usage considerations <br> 1) circuit voltage controller COMS, its great resistance to enter a total, On the interference signal capture ability is strong. Therefore, the unused pin .not vacant, to connect la resistance or pull-down resistors, give it a constant level. <br> 2) input termination signal source low inner resistance, to input and signal source to the current limiting resistor in series between the input 1mA current limit .. <br> 3) when the next long signal transmission line, at COMS circuit terminating matching resistor. <br> 4) when the input termination large capacitance, should the input resistance and capacitance indirect protection. Resistance values are R = V0/1mA .. V0 is external capacitor voltage on. <br> 5) COMS of input current exceed 1mA, it is possible to burn COMS. <br> <br> 7, TTL door circuit input load characteristics (resistors input with special cases of processing) .: <br> 1) vacant equivalent input termination at high level. Because this can be viewed as input termination resistance of an infinity. <br> 2) gate circuit input series 10K resistance after input low level, input a rendering is high level instead .of the low level. Because the TTL door circuit input load characteristics, only enter the termination of the series resistance less than 910 and European input to when it's low level signal can be gate circuits identified series resistance big words input has been rendering high level. .This is important to note. COMS gate circuits do not consider these. <br> <br> 8 TTL circuits have collector OC Mun, MOS also and the collecting electrode corresponding drain of OD door, its output is called open drain output. OC door .in due time have the leakage current output, it is the leakage current, why have the leakage current? that's because when the transistor as its base current is approximately equal to 0, but is not a real is 0, the collecting electrode of the transistor .current that is not a true 0, about 0. And this is the leakage current. <br> Open drain output: the output of the OC door is open drain output; OD door open drain output is the output. It can absorb a lot .of current, but not to the output current. Therefore, in order to be able to input and output current, it's time to use with the power and together with pull-up resistor. OD door General as output buffers / drivers, level translator as .well as meet absorption big load current needs. <br> <br> 9. What is called the totem pole, and what is the difference between a leakage path? <br> TTL IC, the output is connected to the transistor output is called .La totem pole output, no door called OC. Because the TTL is a three-level gateways, totem pole that is two levels are connected to the push-pull tube. So push-pull is a totem. General Totem-output, high level .400UA, low-level 8MA <br> <br> ++++++++++++++++++++++++++++++++++++++ .+++++< br> <br> CMOS devices unused input must be connected to the high level or low level, this is because the CMOS is a high input impedance devices, ideal is not input current. If no input pin is vacant ., is easy to detect interference signals, affecting the logic chip, or even static electricity accumulated run permanent breakdown this input, resulting in chip failures. <br> In addition, only 4000 series of CMOS devices can work in 15 v power supply, such .as 74HC, 74HCT can only work in the 5 v power supply, there are already working in 3 and 2.5 volt power CMOS logic circuit chip. <br> <br> CMOS level and TTL level: <br> CMOS logic level range is relatively .large, in the range of 3 ~ 15V, such as 4000 series when 5V power supply, the output above 4.6 as high output in the following low-level 0.05V. Enter 3.5V above shows the high level, enter the following low-level .1.5V. <br> For TTL chips that power in the range 0 ~ 5V, common is 5V, where 74 series 5V power supply, output in 2.7V above is the high output in the following low-level 0.5V, enter 2V above .is high in the lower-level 0.8V following. Hence, circuit with TTL CMOS circuit will have a level translation, so that the two-level domain value to match. <br> The logic level of a number of concepts: <br> .To understand the logic level of content, you have to know the following concepts: <br> <ol> Input high level (Vih): guaranteed logic gate input for high level allowed by the minimum input high level, when input level higher than Vih ., input level is considered as a high level. Input low level (Vil): guaranteed logic gate inputs as low level maximum input low level, when the input level is lower than the Vil, felt that the input level to low level. Output ( .Voh): ensure output logic gate to the high level of output level of the minimum value, logic gates output for high level level value must be greater than the Voh. Output low level (Vol): ensure output logic gates as low level of the .output level of the maximum output of logic gates as low level level value must be less than this Vol. Threshold level (Vt): digital circuit chip, there is a threshold level, the circuit had just managed to overturn action level. It is a .profession to the Vil, the voltage value between Vih, for CMOS circuits of threshold levels, essentially half of the power supply voltage value, but to guarantee the stability of the output, you must require a high input voltage Vih>, <Vil .low level, and if the input level up or down at the threshold, the Vil-Vih, circuit output is in an unstable state. <br> For general logic level, the relationship between the above parameters are as follows: <br> Voh .Vih>>>> Vol Vil Vt Ioh: logic gate output for high level of load current (a la currents). </ ol> Iol: logic gate output to a low level of load current (sink). Iih .: logic gate input to the high level of current (sink). Iil: logic gate input to a low level of current (for current). <br> The gate circuit output is not received within the integrated unit load resistance and closed as output ., this form of open door door is called. Open-circuit of TTL, CMOS, ECL gate called collector (OC), drain (OD), emission-drain (OE), should be used to review whether connected to La resistance (OC ., OD doors) or pull-down resistor (OE Mun), and resistance is appropriate. For a collector (OC), the pull-up resistor RL should meet the following conditions: <br> (1): RL <(VCC .-Voh) / (n * Ioh + m * Iih) <br> (2): RL> (VCC-Vol) / (Iol + m * Iil) <br> Where n: line and the number of open doors; m is the number .of input. <br> <br> 10: the common logic level <br> Logic level: CMOS, TTL, LVTTL, ECL, PECL, GTL, RS232, RS422, LVDS, etc. With TTL and CMOS logic level according to the .typical voltage can be divided into four categories: 5V series (5V TTL and 5V CMOS), 3.3V series, 2.5V series and 1.8V series. 5V 5V TTL and CMOS logic level is a general purpose logic level. 3.3V and following logic .level is called low-voltage logic level, commonly used as LVTTL level. Low-voltage logic level there are two 2.5V and 1.8V. ECL / PECL and LVDS output is a differential input. RS-422/485 and RS-232 serial .interface standard is, RS-422/485 is a differential input and output, single-ended input output RS-232 is. ++++++++++++++++++++++++ .++++< br> <br> OC door, also known as the collector (open drain) and non-gate circuits, Open Collector (Open Drain). <br> Why introduce OC door? <br> Actual use, sometimes .it takes two or more NAND output connection on the same wire, the NAND on data (status level) in the same wire transfer out. Therefore, you need a new NAND gate circuit - OC to achieve "line and logic". <br .> OC door is mainly used in three ways: <br> <ol> Realization and or non-logic level translation, done by doing a drive. Due to the OC gate circuits of the output pipe for the collecting electrode dangling, use need external .Rp a pull-up resistor to the power supply VCC. OC door using a pull-up resistor to output, in addition to increase output pin drive capability, pull-up resistor selection principle, from the lower power consumption and chip sink capacity considerations should .be large enough to ensure adequate; from the driving current account should be small enough. Line with the logic, the two output (including the two above) direct interconnection can achieve "AND" logic function. In bus transport and other practical applications require multiple .gate output parallel connection used, and the General output TTL gates and cannot directly and then use the door between the output due to the low impedance puts a lot of short circuit current (sink), while the burning device. Available in hardware, OC or .3-door (ST gate). Realization with OC door and that line in the output port should be added a pull-up resistor. 3-door (ST gate) is mainly used in applications to multiple gate output shared data bus, in order .to avoid multiple gate output while consuming data bus, these doors enable signal (EN) only allows one to effective level (such as high level), because the output of the 3-door is the push-pull output of low resistance, and do .not need to connect la (load) resistance, so switching speed is faster than the OC door, often used with 3-door as output buffers. </ ol >++++++++++++++++ .+++++++++++++++++++++< br> What is OC, OD? <br> Collector Mun (collector-drain OC or OD) <br> Open-Drain is .open-drain output, equivalent to the collector (Open-Collector) output, ie the TTL in the open collector output (OC). Generally used to line or, line and also for the current drive. <br> Open-Drain is on .MOS, Open-Collector is bipolar pipe, use nothing different. <br> Open drain form of circuit has the following characteristics: <br> A. use external circuit drive capability, reduced IC internal actuation. Or driven than chip power voltage high load .. <br> B. you can apply more than one open drain output pin connected to a line. Through a pull-up resistor, without adding any devices, formation logical "and" relationship. This is the I2C, SMBus, bus bus uses .state of the judgment. If a totem output must be connected to the tensile resistance. Add capacitive load, the decline in the yen is the chip, is a source of transistor drive, a faster rise in the yen is passive; the external resistor, .slow. If you require speed to high resistance is small, the consumption is high. So load resistance of choice to balance power and speed. <br> C. you can use to change the voltage on the La power, change the transport level. .For example, coupled with the pull-up resistor can provide TTL / CMOS-level output, etc. <br> D. open drain Pin is not connected to an external pull-up resistor can only output low level. Generally speaking, open drain .is used to connect to a different level of the device, the match level. <br> Normal CMOS output level is up, down two tube, remove the top of the tubes is OPEN-DRAIN. The main purpose of output has two: level .switchHeat exchanger and lines. <br> Because of the leakage level open circuit, so after the level circuit must receive a pull-up resistor, pull-up resistor power supply voltage to determine output level. So you can make any level of conversion. .<br> Line and function is primarily used to have several circuits on the same signal to lower the operation, if this circuit does not want to pull the output low, high, because the pipe is above OPEN-DRAIN take off, high level depends .on external pull-up resistor. (Normal CMOS output level, if there is one output for high and another to low, equal to the power circuit.) <br> OPEN-DRAIN provides flexible output mode, but also has its weaknesses, is .bringing the rising edge of the delay. Because of the rising edge is through an external connected to La passive resistance on load charging when resistance to select hour delay on the small, but power consumption; conversely large power small delay. So if you have to .delay, suggested to drop along the output. <br>.